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[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
Platform: | Size: 110592 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] SPI3_8bit

Description: 一整套通用的用Verilog代码实现的SPI3接口（8bit接口）协议代码，包含ISE工程文件，本代码在Xilinx公司的FPGA上实现，并且有Modelsim仿真的源文件-SPI3 verilog code（including ISE project and modelsim code)
Platform: | Size: 2829312 | Author: yaofan | Hits:

[VHDL-FPGA-Verilog] all

Description: 基于FPGA的频率测试器的verilog HDL代码，测试范围1-10MHz，用XILINX公司的ISE软件打开。-Based on FPGA-frequency test the Verilog HDL code, test range 1-10MHz, with XILINX ISE software to open.
Platform: | Size: 2466816 | Author: elink | Hits:

[VHDL-FPGA-Verilog] VCO

Description: 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
Platform: | Size: 1024 | Author: 法克尤 | Hits:

[VHDL-FPGA-Verilog] comparator

Description: 使用verilog语言，在FPGA开发工具ISE上实现比较器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the comparator function.
Platform: | Size: 629760 | Author: 丁帅 | Hits:

[VHDL-FPGA-Verilog] flip_flop

Description: 使用verilog语言，在FPGA开发工具ISE上实现触发器功能。-The use of Verilog language, in FPGA ISE development tools to achieve the flip-flop function.
Platform: | Size: 161792 | Author: 丁帅 | Hits:

[Other] calculator

Description: 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages ​ ​ Verilog, developing software ISE, according to the ucf file to sort out the pin relationship. Application need to have some knowledge of the development board and fpga design!
Platform: | Size: 3531776 | Author: QIAO | Hits:

[assembly language] Useful_data

Description: Full flow description of the flow of developing the verilog code in ISE and steps in implementing and executing in fpga
Platform: | Size: 212992 | Author: kanth | Hits:

[VHDL-FPGA-Verilog] EMAC6

Description: verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.
Platform: | Size: 3602432 | Author: trygov | Hits:

[source in ebook] CooperativeCommunication

Description: 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several different system model of cooperative diversity and cooperative diversity protocol 3 space-time block code codec and collaborative communication using the Verilog hardware description language to achieve ISE Integrated environment and comprehensive simulation results correctly downloaded to the FPGA circuit board observed with an oscilloscope output data is correct, verify empty block codes collaborative communication performance.
Platform: | Size: 10552320 | Author: 牧童 | Hits:

[VHDL-FPGA-Verilog] run_led

Description: Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
Platform: | Size: 304128 | Author: zy | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a serial port development of classic routines.
Platform: | Size: 219136 | Author: 韩建平 | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 6000640 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] pll

Description: 一个基于FPGA的载波同步环的设计，开发语言Verilog，开发工具ISE 14.7，可用于FM接收机中，典型SDR项目-An FPGA-based carrier synchronization loop design, development language Verilog, development tools ISE 14.7, FM receivers can be used, typically SDR project
Platform: | Size: 2273280 | Author: 郭永峰 | Hits:

[VHDL-FPGA-Verilog] 1-example_led_4

Description: Verilog编写的计数闪灯，FPGA实验板，Xilinx ISE实验环境-Verilog prepared by flash count, FPGA experimental board, Xilinx ISE experimental environment
Platform: | Size: 178176 | Author: 华强 | Hits:

[VHDL-FPGA-Verilog] 1-example_led_5

Description: Verilog编写的移位闪灯（跑马灯），FPGA实验板，Xilinx ISE实验环境-Verilog prepared by a shift flash (marquees), FPGA experimental board, Xilinx ISE experimental environment
Platform: | Size: 237568 | Author: 华强 | Hits:

[Other] i2c_lightsensor

Description: 用Verilog HDL编写的光敏传感器AD/DA程序，AD结果显示在LCD上，DA结果控制LED的亮度，相关软件：ISE Design suit，硬件：xilinx FPGA开发板-Verilog HDL prepared with light sensors AD/DA program, AD results are displayed on LCD, DA of controlling LED brightness, software: ISE Design suit, hardware: xilinx FPGA development board
Platform: | Size: 759808 | Author: renyini | Hits:

[VHDL-FPGA-Verilog] my_i2c

Description: 基于FPGA的i2c通信，使用Verilog hdl实现，带有功能说明文档、ise工程、modelsim仿真工程-i2c communication based FPGA using Verilog hdl implementation, with the function documentation, ise project, modelsim simulation project
Platform: | Size: 7451648 | Author: 刘省伟 | Hits:
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